The present invention relates to a semiconductor memory device in which a memory cell array is constructed of the same memory cells as DRAM (dynamic random access memory), and moreover which when viewed from outside the semiconductor memory device, operates with the same specifications as SRAM (static RAM). In particular, the present invention relates to a semiconductor memory device which is compatible with SRAM in which a write enable signal for determining the write timing for a memory cell is supplied asynchronously relative to a write address.
SRAM and DRAM are the most representative examples of semiconductor memory devices to which random access is possible. In comparison with DRAM, SRAM is generally faster, and provided a power source is supplied and an address is input, the internal sequential circuit will operate so as to detect any address transitions, and perform reading and writing. In this manner, because SRAM is operated simply by provision of an input signal waveform which is simple in comparison with DRAM, the construction of the circuit for generating the input signal waveform can also be simplified.
Furthermore, because SRAM does not require a refresh for continued retention of data stored in the memory cells as DRAM does, SRAM offers the advantages that handling is easy, and moreover because a refresh is unnecessary, the data retention current in standby mode is very small. For the above reasons, SRAM is widely used in a variety of applications. However, because SRAM typically requires six transistors for each memory cell, the chip size is always larger than for DRAM, and the cost of SRAM is also higher than for DRAM.
In contrast, DRAM suffers from a more complex timing control than SRAM, in that an address needs to be split in two and provided as a separate row address and column address, and a RAS (row address strobe) signal and a CAS (column address strobe) signal are required as signals for defining the latch timing of these addresses, and a control circuit for regular refresh of the memory cells is required.
Furthermore, DRAM suffers from the problem that even when there is no access from externally, the current consumption is large due to the requirement to conduct a refresh of the memory cells. Having said that, a memory cell of a DRAM can be constructed from a single transistor and a single capacitor, and so a shift to mass storage with a small chip size is relatively easy. Consequently, in constructing semiconductor memory devices of identical storage volume, DRAM will be cheaper than SRAM.
Up until now, SRAM has been the mainstream semiconductor memory device used in portable apparatus such as portable telephones. The reasons for this include the fact that up until now portable telephones have been provided with only simple functions and so large storage semiconductor memory devices have been unnecessary, the fact that SRAM is simpler to handle than DRAM in terms of timing control and the like, and the fact that SRAM has only a small standby current and offers low power consumption and so is more suitable for portable telephones and the like in which extending continuous talk time and continuous standby time is a priority.
However recently, portable telephones which offer a huge number of functions have started appearing, and functions such as the ability to send and receive email, or the ability to access various sites and obtain, for example, general information about local restaurants are now a reality. Moreover, in the most recent portable telephones, functions to enable access to web servers on the internet and the subsequent display of simplified versions of the content of home pages have appeared, and it is envisaged that in the future, access to internet home pages and the like in the same manner as conventional desktop type personal computers will be possible.
In order to realize such functions, the type of simple text display used on conventional portable telephones will be insufficient, and graphic displays for providing a variety of multimedia information to the user will be essential. This will require the temporary storage of large amounts of data received from a public network or the like in semiconductor memory devices housed inside the portable telephone. That is, it is thought that mass storage such as that provided by DRAM will be a necessity for the semiconductor memory devices used in future portable telephones. Moreover, because small size and light weight are two essential conditions for portable apparatus, even if the storage capacity of the semiconductor memory devices used is increased, any increases in size or weight of the apparatus must be avoided.
As described above, consideration of ease of handling and power consumption would suggest SRAM as the preferred semiconductor memory device for use in portable apparatus, but from the viewpoint of mass storage DRAM is preferable. That is, it can be said that for future portable apparatus, a semiconductor memory device which incorporates the advantages of SRAM and DRAM is ideal. An example of such a semiconductor memory device known as pseudo SRAM, which uses the same memory cells as those used by DRAM but which has almost the same specifications as SRAM when viewed from externally, has already been proposed.
Pseudo SRAM does not require addresses to be provided as a separate row address and column address as is the case with DRAM, and furthermore timing signals for these such as RAS and CAS are also unnecessary. Hence with pseudo SRAM, an address is provided at a single time, in the same manner as for standard SRAM, and a chip enable signal corresponding with the clock of a clock synchronous type semiconductor memory device is used as a trigger for latch of an address and the performing of reading or writing.
However, pseudo SRAM is not completely compatible with standard SRAM, and most pseudo SRAM is equipped with a refresh control terminal for controlling the refresh of the memory cells from externally, and the control of the refresh must be controlled from outside the pseudo SRAM. Consequently, in comparison with SRAM, most pseudo SRAM is not particularly easy to handle, and suffer from requiring an extra circuit for refresh control. As a result, pseudo SRAM in which external control of the refresh is unnecessary and which is operated with exactly the same specifications as standard SRAM is also under consideration, as described below. However, as described below, this type of pseudo SRAM also suffers from several drawbacks.
As a first background art example there are the semiconductor memory devices disclosed in Japanese Unexamined Patent Application, First Publication No. Sho-61-5495 and Japanese Unexamined Patent Application, First Publication No. Sho-62-188096. A semiconductor memory device of the former application incorporates an integrated refresh timer for timing the refresh interval, and at the point where a time equivalent to the refresh interval has elapsed, a refresh start request is generated, and following completion of the amplification operation of a bit line pair during a read operation, the word line corresponding to the refresh address is activated and self refresh is performed. By so doing, the need for controlling the refresh of the memory cells from outside the semiconductor memory device disappears.
Furthermore the semiconductor memory device of the latter application specifically discloses a detailed construction for an operation timing control circuit required for realizing the semiconductor memory device of the former application, and in effect is the same semiconductor memory device as that disclosed in the former application.
As a second background art example there is the semiconductor memory device disclosed in Japanese Unexamined Patent Application, First Publication No. Hei-6-36557. This semiconductor memory device is also provided with an internal timer for conducting refresh operations, and at the point where a predetermined refresh time has elapsed, a refresh start request is generated, and following completion of a read operation, a self refresh operation is performed.
However, in both the first and second background art examples, absolutely no consideration is given to the timing with which the write enable signal for determining the write timing is provided, and consequently there is a possibility of the following type of problems developing. Namely, in the case where pseudo SRAM is operated under the same specifications as standard SRAM, then the write enable signal will be provided asynchronously relative to an address transition. Moreover, also the self refresh due to a refresh start request, will be performed asynchronously relative to an address transition. As a result, the write enable signal will be input with a later timing than the refresh start request, and in those cases where, for example, the write enable signal is made valid in the latter portion of the memory cycle, if the self refresh has already started then write cannot be performed until after completion of this self refresh.
However, if this happens, the write following the self refresh will be delayed significantly. In order to avoid this type of situation it is necessary for write operations to have priority over self refresh operations. However, so doing means that in those cases where following the generation of a refresh start request a plurality of write requests are generated continuously, there is no room for conducting the self refresh, and so there is a possibility that performing the self refresh will be impossible.
Furthermore, in both the first and second background art examples, in those cases where an address incorporates a skew, a problem of delayed access arises. Namely, in those cases where a skew exists in an address, there is a need to surely delay the word line selection operation by a portion corresponding to the skew. This is because the DRAM memory cells used by pseudo SRAM are typically of destructive read type, and when a certain word line is activated and reading performed by a sense amplifier, there is a necessity for the data originally stored in all of the memory cells connected to the word line to be written back from the corresponding sense amplifiers to the memory cells.
As a result, once a read has commenced, the word line cannot be switched to another word line until the rewrite corresponding to the read has been completed. However, in those cases where the address incorporates a skew, this is equivalent to a transition in the address value, and so as a result the activated word line will be switched. Consequently, a plurality of word lines will be activated simultaneously, and the data in the memory cells connected to these word lines will be read on the same bit line, resulting in the destruction of the memory cell data.
In order to prevent this type of situation, as described above, it is necessary to delay the activation of the word line by the skew included in the address. As a result, if a refresh is performed after a read operation, then in the case where the skew is particularly large, the start of the refresh will also be delayed by the time by which the word line selection operation was delayed due to the existence of the skew, and moreover read operations and so forth following the refresh will also be delayed.
As a third background art example there is the semiconductor memory device disclosed in Japanese Unexamined Patent Application, First Publication No. Hei-4-243087. In this background art example, a refresh timer is not provided within the pseudo SRAM itself, but rather a timer is provided externally to the pseudo SRAM. Then, at the point of a first access request after a refresh time has elapsed, an OE (output enable) signal is produced outside the pseudo SRAM, and following completion of a refresh in accordance with the OE signal, the read or write operation is performed in accordance with the access request.
However, in the construction of this third background art example, the power consumption becomes excessively high, making it inapplicable to lower power consumption products such as portable telephones which are built on the premise of long usage cycles under battery driven conditions. In this third background art example, at the time that a chip enable (CE) signal becomes valid, a pseudo SRAM is operated by latching an address input from outside. That is, in the third background art example, each time the pseudo SRAM is accessed the chip enable signal must be activated, and so the charge and discharge current of the chip enable signal bus lines wired on to a printed circuit board results in high power consumption.
In addition, a fourth background art example is the semiconductor memory device disclosed in Japanese Patent Publication No. 2529680 (Japanese Unexamined Patent Application, First Publication No. Sho-63-206994). In this background art example, a construction is disclosed which is identical with conventional pseudo SRAM in which refresh operations are controlled from externally, and another construction which offers improvements on this pseudo SRAM construction is also disclosed.
In the former construction, on reception of the fact that the output enable signal is valid, an address transition detection signal is generated, and following completion of a self refresh in accordance with a refresh address generated inside the pseudo SRAM, then when the output enable signal becomes invalid, another address transition detection signal is generated, and a refresh is performed on the external address provided from outside the pseudo SRAM. However, if the output enable signal is generated regularly after every refresh interval, then the latter refresh of the external address is essentially unnecessary, and so the refresh of the external address produces a wasted consumption of power.
In contrast, in the latter construction of the fourth background art example, transitions are detected in an external address and an address transition detection signal generated, and a refresh is then performed on a refresh address generated inside the pseudo SRAM in response to the address transition detection signal. Then, following the elapsing of a set time, another address transition detection signal is generated, and normal reading or writing is performed with the external address as the subject. However, problems arise with this construction when the external address incorporates a skew.
Namely, in those cases where the external address incorporates a skew, because each bit of the address will vary by different timings, an address transition will be detected at each of the timings, and a plurality of address transition detection signals will be generated. As a result, although the starting a refresh in response to the first such address transition detection signal is alright, the second and subsequent address transition detection signals will result in the commencement of normal access of the external address which rightfully should be performed following completion of the refresh operation. Thus, in such cases, even though a refresh operation is in progress, an access request is made of the external address. Consequently, as was pointed out in the description of the first and second background art examples, a plurality of word lines are activated simultaneously, and because the data of the memory cells connected to these word lines will be read on the same bit line, destruction of the memory cell data will result.
In addition to the problems described above, conventional pseudo SRAM devices also suffer from the following problem. Namely, in standard SRAM, often a standby mode is provided whereby supply of electrical power to the internal circuits can be stopped and the power consumption significantly reduced. However in pseudo SRAM, because the memory cells are of the same type as those found in DRAM, continual refresh is required to retain the data stored in the memory cells. As a result, although pseudo SRAM can be said to operate in the same manner as SRAM, a standby mode such as that used in standard SRAM is not provided in conventional pseudo SRAM.
However, in addition to operating pseudo SRAM under identical specifications to standard SRAM, from a convenience viewpoint it would also be extremely desirable to provide pseudo SRAM with a lower power consumption mode similar to the standby mode of standard SRAM. Furthermore, considering the recent marked increase in the functions of portable telephones and the like, it is envisaged that pseudo SRAM will be applied to a variety of uses.
As a result, it is also envisaged that the control which can set a device to a simple standby mode as in standard SRAM will be insufficient in the future. Consequently, it is necessary to pre-empt this situation and propose a standby mode unique to pseudo SRAM which offers functions unavailable in existing standard SRAM. If the power consumption in this standby mode could be controlled in a fine stepwise manner in accordance with the needs of the user or the application being used, then this would be extremely useful.
Furthermore because refresh has been considered a prerequisite in standard DRAM, the concept of standby has not existed, but of course the demand for lower power consumption exists, even for standard DRAM. Consequently, if the concept of standby could be incorporated into standard DRAM, and power consumption reduced by controlling the power consumption in the standby state in a fine stepwise manner in accordance with the needs of the user or the application being used, then new fields of application for standard DRAM could be developed.
The present invention takes into consideration the above mentioned points with the object of providing a semiconductor memory device wherein there are no problems such as normal access being influenced by refresh, refresh unable to be performed due to continuation of writing, defects due to delayed access and destruction of data stored in memory cells occurring in a case where the address includes skew do not occur, and furthermore which operates with the specification of a standard SRAM, and even though storage capacity is increased it has a small chip size, low power consumption and is inexpensive. Moreover, it is an object of the present invention to provide a semiconductor memory device that has standby modes equivalent to those used in standard SRAM, and a unique low power consumption mode, which is not provided in existing semiconductor memory devices. Other objects of the present invention than those mentioned above will become clear from the description of the following embodiments.
The semiconductor memory device of the present invention generates an address transition detection signal in response to an input address signal, and performs memory cell refresh corresponding to the refresh address signal in response to this address transition detection signal, and memory cell access corresponding to the input address signal, in this order.
In this way, by performing access after performing refresh, then even when writing is continuous, refresh can be carried out in a memory cycle. Furthermore, when for example writing is performed to memory cells, then even if the write enable signal is input with a delay, refresh and write do not interfere, and hence timing design can be simplified obviating an increase in circuit size.
Moreover, even when the input address signal incorporates a skew, since the respective bits of the input address signal are changed at different timing due to the skew, concern that a plurality of address transition detection signals are produced and the data of the memory cell is destructed also disappears. Furthermore, since it is no longer necessary to take counter measures such as delaying the access start to the memory cell in order to avoid this problem of memory cell destruction, there is no longer delays inside the semiconductor memory device, thus enabling higher speeds.
The semiconductor memory device of the present invention incorporates a semiconductor memory device which uses a row address and a column address generated from the input address signal, and accesses the memory cell indicated by the input address signal. Therefore, it is no longer to necessary to acquire an address which has been split in two in accordance with the RAS/CAS timing signal as with a standard DRAM, and a one time application of the input address signal is sufficient. Therefore the circuit configuration for generating the signal waveform which is to be input to the semiconductor memory device can be simplified.
Furthermore, since refresh is performed within one memory cycle accompanying the application of the input address signal from outside the semiconductor memory device, then if only an input address signal necessary to refresh all of the memory cells is applied, data of the memory cells can continue to be maintained without performing refresh control from outside the semiconductor memory device, and hence handling is facilitated as with the standard SRAM.
Furthermore, if for the memory cell, one with a single transistor and a single capacitor as with a DRAM is used, then the cell area can be significantly reduced compared to a standard SRAM requiring six transistors per memory cell. Therefore it becomes possible to reduce the chip size and lower cost, while maintaining a large capacity.
Moreover, in the present invention, the transition of the input address signal is made a trigger, and the memory cell is accessed is by taking in the input address signal. Therefore as with the existing pseudo SRAM, there is no longer the requirement for example to change the signal such as the chip enable signal which is provided with the address latch timing control function each time the address is taken in. Hence power consumption can be reduced by this amount.
Here, in the present invention, the upper predetermined bits of the input address signal are used for address transition detection. Moreover, for the plurality of memory cells for which the upper predetermined bits of the input address signal are the same, the page address comprising the bits other than the upper predetermined bits is changed, and these memory cells may be continuously accessed. As a result, a function similar to page mode used in standard DRAM and the like can be realized.
Furthermore, in the present invention, the address transition detection signal may be generated in response to an activation signal which becomes valid when the semiconductor memory device is accessed. For the activation signal, a signal which has the activation function of the chip and which does not have the address latch timing control function may be used. As a result, by setting a previously input address signal, and shifting the activation signal from an invalid state to a valid state, usage such as starting operation inside the semiconductor memory device is possible.
Furthermore, in the present invention, a one shot pulse which has a pulse width corresponding to a waiting period from when the input address signal begins to change until said input address signal becomes definite, may be generated as the address transition detection signal. Moreover, in the semiconductor memory device of the present invention, refresh may be performed within the period when the one shot pulse is being generated. By so doing, the period in the standard SRAM which is originally the waiting period, can be effectively used to perform refresh. Moreover, also when refresh is not performed from when refresh of one refresh cycle is completed until the next refresh cycle, since the period of the one shot pulse corresponds to the waiting period as with the standard SRAM, the time necessary for reading from the memory cell can be made constant, irrespective of whether or not refresh is performed.
Furthermore, in the present invention, when the write enable signal is input within the period for performing refresh, the input write data may be taken in to the bus, and after completion of refresh, the write data may be written into the memory cell from the bus. Moreover, in the semiconductor memory device of the present invention, when the address transition detection signal is generated while self refresh is being performed, once self refresh has been performed, access for the input address signal made be performed. By so doing, even when the input address signal is being applied during self refresh, the input address signal does not influence the self refresh, and the operation results where access is always performed after performing self refresh. Therefore the logical design operation which becomes necessary for timing control can be simplified.
Moreover, in the present invention, when the address transition detection signal is not generated over the predetermined period, self refresh may be started and refresh performed at a fixed time intervals. If normal, the input address signal is applied a certain number of times, and the accompanying memory cell proceeds towards refresh.
However due to the above, even if the input address signal is not applied over a long period, the data stored in the memory cell can be held continuously. Furthermore, in the present invention, of the two kinds of transition points corresponding to the rising or falling of the one shot pulse, preferably the other transition point different to the transition point which becomes the trigger for starting the refresh is made a trigger, and the refresh address updated. As a result, when the newly input address signal changes and the next memory cycle is started, then even if a skew is contained in the input address signal, since the refresh address is already set in the preceding memory cycle, the selection operation of the memory cell (word line) which becomes the object of the refresh is completed without being delayed by the influence of skew, and without the occurrence of a delay in the refresh.
Moreover, in the present invention, by inputting a test mode signal, and also inputting an input refresh request at a desired timing, the refresh operation inside the semiconductor memory device can be freely controlled from the outside. Therefore, it is possible to examine for the presence of a defect produced by noise in the row enable signal which controls the refresh, and noise in a pair of the bit line in the interval from when the word line is activated until the sense operation of the sense amplifier is started, due for example to the influence of the one shot pulse generated from the change in the input address signal. Besides this, since the test mode signal is set by supplying a refresh request from the outside, and if a refresh request is not input from the outside, refresh is not fully performed in the semiconductor memory device, then a condition which inhibits refresh for hold testing can be easily realized.
Furthermore, in the present invention, preferably the input refresh request is applied via a pin which is not used during refresh. By so doing, the pin for applying the input refresh request and a pin for inputting an output enable signal or the like can be shared. Consequently, this is settled without assigning a new pin for merely applying the input refresh request.
Moreover, in the present invention, as well as being able to read and write after performing refresh, it is also possible when a write request is input, to write to the memory cell after performing refresh, and when a read request is input, to perform refresh after reading. By having the latter, reading can be sped up, enabling an improvement in access time. Therefore, preferably read/write is judged when a predetermined time has elapsed from a change in the input address signal.
Furthermore, the control circuit according to the present invention supplies a control signal or an address signal from outside of the memory chip which forms the memory cell, and together with this memory chip constitutes the abovementioned semiconductor memory device.
For the test method of a semiconductor memory device according to the present invention, when a predetermined test pattern is written in to the memory cell array, all of the refresh is inhibited by the refresh request generated inside the semiconductor memory device, and the transition timing of the input address signal and the supply timing of the input refresh request are set with a certain time relationship, and the input refresh request is applied and refresh of a memory cell array performed while changing the input address signal, and by collating the test pattern which has previously been written in and the data of the memory cell array, quality judgment of the semiconductor memory device is performed. As a result, it is possible to examine for the presence of a defect produced by noise in the row enable signal which controls the refresh, and noise in a pair of the bit line in the interval from when the word line is activated until the sense operation of the sense amplifier is started, due to the influence of the address transition detection signal (one shot pulse) generated from the change in the input address signal.
Moreover, in the test method of the present invention, the time relationship between the transition timing of the input address signal and the supply timing of the input refresh request may be changed over a predetermined time range. For example, by making all the time ranges considered taken as the time relationship for between the two timing intervals, the above mentioned predetermined time range, then no matter what the time relationship is between these timing intervals, it can be guaranteed that deficiencies attributable to the above mentioned noise will not occur.
Furthermore, in the test method of the present invention, when the input address signal is changed, all of the bits of the input address signal may be simultaneously inverted. By so doing, the noise is able to be easily generated in the row enable signal or the bit line pair etc. and the magnitude of the noise is also increased. Therefore, it is possible to examine for whether or not deficiencies will arise even under these severe conditions.
In the semiconductor memory device according to another aspect of the present invention, when a standby state results, then in accordance with the mode selected from amongst a plurality of kinds of modes, the respective circuits inside the device which are necessary for the self refresh are driven for each of the circuits, or drive thereof is stopped. As a result, there is no longer the need to operate unnecessary circuits in performing the refresh, and hence power consumption can be reduced. Therefore in a standard SRAM specification memory, a pseudo SRAM, a standard DRAM or the like which use a memory cell which requires refresh, a low power consumption mode can be realized similar to the standby mode in a standard SRAM. Furthermore, since it is possible to control whether or not to operate the respective circuits for each of the circuits necessary for self refresh, it is possible to realize a unique standby mode not provided in a standard SRAM etc., where the standby current is reduced stepwise corresponding to the needs of the user or the application.
Furthermore, in the present invention, when the memory cell array is constructed with a plurality of memory cell areas which control independent refresh operations, then preferably a mode is set for each memory plate comprising the memory cell area and the peripheral circuits thereof, to operate the respective memory plates or stop the operation thereof. As a result, in relation to a memory cell area which stores information that should be held temporarily, it is not necessary to perform self refresh in the standby state. Consequently, if whether or not to operate a memory plate is determined corresponding to the assignment of the memory space which an application or the like uses, the standby current can be kept to a minimum for the needs of a user or the form of the application.
Moreover, in the present invention, a power supply circuit shared between a plurality of memory plates may be provided, and whether or not to perform power supply from this power supply circuit to the respective memory plates may be individually controlled corresponding to the mode set for each memory plate. As a result, the size of the power supply circuit does not increase in proportion to the number of memory plates. Hence even if a large number of memory plates are provided, the standby current can be reduced by the small scale circuit structure.
Furthermore, in the present invention, it is preferable to be able to set the mode for each of the memory plates by applying an input mode signal for standby. As a result, even if the needs of the user, or the application being used is changed, the standby current can be kept to a minimum while flexibly corresponding to the change.
Moreover, in the present invention, the memory plate which is to perform mode setting may be specified based on the address which is input for mode setting. As a result, compared to when for example mode setting is performed as a result of disconnection of a fuse, mode setting can be easily performed, and mode resetting can be easily performed on the user side similarly to the normal read and write. Consequently, it is not necessary to apply an exclusive signal from outside for mode setting. Also it is not necessary to provide a pin for this exclusive signal.
Furthermore, in the present invention, a first mode may be provided for operating both the refresh control circuit and the power supply circuit, a second mode may be provided for stopping operation of the refresh control circuit and operating the power supply circuit, and a third control mode may be provided for stopping the operation of both the refresh control circuit and the power supply circuit, and any of the modes may be selected from amongst these. As a result, according for example the equipment to be used or the use environment thereof, it is possible to finely control from outside, the necessity or not for data holding in the standby state, the time for recovery to the active state, the current consumption, and so on. That is to say, in the first mode, the data of the memory cell can be held because the current to the necessary circuits in self refresh is supplied, and the time from the standby state until shifting to the active state can be made the shortest amongst the three kinds of modes. Furthermore, in the second mode, as well as being able to reduce the consumption current more than for the first mode by the amount to be supplied to the refresh control circuit, when shifting from the standby state to the active state, the semiconductor memory device can be immediately used as with the first mode. Moreover, in the third mode, the consumption current can be made a minimum of the three kinds of modes.
Furthermore, in this case, when with respect to a predetermined address, there is a request to write data which is previously determined for each of the modes, or when there is a predetermined change in the activation signal, mode setting may be performed. As a result, it is not necessary to apply an exclusive signal to the semiconductor memory device for setting the standby mode. Furthermore, it is not necessary to provide a pin for this exclusive signal in the semiconductor memory device.